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AD5379
PARALLEL INTERFACE
V
CC
= 2.7 V to 5.5 V; V
DD
= 11.4 V to 16.5 V; V
SS
= 11.4 V to 16.5 V; AGND = DGND = DUTGND = 0 V; V
REF
(+) = 5 V;
V
REF
(
) =
3.5 V, FIFOEN = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter
1, 2, 3
Limit at T
MIN
to T
MAX
Unit
t
0
4.5
ns min
t
1
4.5
ns min
t
2
10
ns min
t
3
10
ns min
t
4
0
ns min
t
5
0
ns min
t
6
4.5
ns min
t
7
4.5
ns min
t
8
20
ns min
t
9
240
ns min
t
104
0/30
ns min/max
t
114
330
ns max
t
12
0
ns min
t
13
30
ns min
t
14
20
ns min
t
154
150
ns typ
t
16
20
ns min
t
17
0
ns min
t
18
100
ns typ
t
19
20/30
μs typ/ max
t
20
10
ns min
t
21
350
ns max
t
22
10
ns min
t
23
120
μs max
Rev. 0 | Page 9 of 28
Description
REG0, REG1, Address to WR Rising Edge Setup Time.
REG0, REG1, Address to WR Rising Edge Hold Time.
CS Pulse Width Low.
WR Pulse Width Low.
CS to WR Falling Edge Setup Time.
WR to CS Rising Edge Hold Time.
Data to WR Rising Edge Setup Time.
Data to WR Rising Edge Hold Time.
WR Pulse Width High.
Minimum WR Cycle Time (Single-Channel Write).
WR Rising Edge to BUSY Falling Edge.
BUSY Pulse Width Low (Single-Channel Update). See Table 10.
BUSY Rising Edge to WR Rising Edge.
WR Rising Edge to LDAC Falling Edge.
LDAC Pulse Width Low.
BUSY Rising Edge to DAC Output Response Time.
LDAC Rising Edge to WR Rising Edge.
BUSY Rising Edge to LDAC Falling Edge.
LDAC Falling Edge to DAC Output Response Time.
DAC Output Settling Time.
CLR Pulse Width Low.
CLR/RESET Pulse Activation Time.
RESET Pulse Width Low.
RESET Time Indicated by BUSY
Low.
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 6.
4
Measured with load circuit in Figure 2.
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